In a memory subsystem that operates in a source synchronous manner, the device that transmits a data signal on a conductive data line also transmits a strobe signal on a separate conductive line. A pulse in the strobe signal has a predefined phase relationship to each associated pulse in a number of data signals. The pulse in the strobe signal is used to capture bit values in the data signals at the receiving device. In particular, the data and strobe signals are run through receiver circuitry that detects the logic levels that are being asserted, and translates them into voltage levels that are suitable for processing by controller circuitry in an integrated circuit (IC) die. The outputs of the receiver circuitry are then fed to a number of latches each of which captures a bit value in a respective data signal in response to a pulse in the strobe signal.
For example, Double Data Rate (DDR) memory devices use source synchronous transfers when data is read from the memory devices. The data strobe signal (DQS) is sent along with the data (DQ) to be clocked. The clocking edges of the DQS signal are coincidental with the data transition time. To capture the data in a register using the DQS signal, the DQS signal needs to be delayed to satisfy the data set-up time requirement of the register.
Conventional memory interfaces use a delay locked loop (DLL) for clock recovery. One configuration is based upon self-biasing techniques in which all bias voltages and currents are referenced to other generated bias voltages and currents. Another configuration is based upon a dual loop DLL architecture for continuously running clock. One loop generates eight equally spaced reference clocks, and the other loop multiplexes between selected successive reference clocks to generate the desired recovered clock. More precision is desired however to place the strobe in the middle of the data eye to maximize system timing margin.